Electric-field-assisted assembly enables scalable, lithography-free fabrication of logic circuits using 2D semiconductors. It provides a practical route to high-performance electronics beyond conventional silicon processing.
(Nanowerk Spotlight) The future of computing may hinge on how precisely we can place atomically thin materials.
As the components of microprocessors continue to shrink, engineers face limits that are no longer just economic or technical but physical. The transistors that drive digital logic are now fabricated at scales approaching a few dozen atoms. Etching ever-smaller features into silicon risks electrical interference, current leakage, and fabrication steps so complex they may no longer be sustainable. The long-successful strategy of packing more transistors into the same chip area is approaching a point where traditional methods can no longer deliver consistent gains.
This constraint has pushed researchers to explore materials that can operate reliably at much smaller scales. Two-dimensional semiconductors are materials that can be sliced down to a single atomic layer. Some of these, including molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂), are especially promising. They support efficient charge transport even when made extremely thin and can be tuned to carry either electrons or holes. This makes them suitable as n-type and p-type transistors, the two building blocks required for complementary logic circuits.
But performance alone is not enough. While many of these materials function well as isolated transistors, building circuits from them has proven difficult. Existing methods for making 2D devices either require high-temperature synthesis in vacuum chambers or involve manual placement of nanosheets using micromanipulators. Neither approach is compatible with large-scale production.
Attempts to scale up have led to inconsistent device quality, poor alignment, or complex multi-step fabrication processes that undermine the simplicity these materials are supposed to offer.
A study published in Advanced Functional Materials (“Complementary Logic Driven by Dielectrophoretic Assembly of 2D Semiconductors”) presents a different solution. The researchers developed a method that combines solution-based exfoliation of 2D semiconductors with electric-field-guided assembly. This process allows both n-type MoS₂ and p-type WSe₂ nanosheets to be positioned precisely between predefined electrodes, forming complementary logic circuits without lithography, etching, or high temperatures. All assembly occurs in parallel. This supports multiple devices on the same chip in a single step.
Fabrication of complementary logic circuits via alternating current dielectrophoresis (AC-DEP)-assisted deterministic assembly of solution-processed 2Dsemiconducting nanosheets. a) Electrochemical exfoliation process for producing 2D MoS2 and WSe2 nanosheets. b) AFM images of exfoliated MoS2 and WSe2 nanosheets. c) Schematic illustration of the AC-DEP assembly process for fabricating MoS2 and WSe2 channel arrays. The black lines in the top right schematics represent electric field lines, while the green arrows indicate the directions of the dielectrophoretic force on MoS2 and WSe2 nanosheets. d) False-colored SEM images of MoS2 and WSe2 channels created by AC-dielectrophoresis. (Image: Reprinted from DOI:10.1002/adfm.202516285, CC BY) (click on image to enlarge)
The process begins by producing high-quality 2D nanosheets from bulk crystals. Instead of using harsh sonication methods that fragment the material, the team uses electrochemical exfoliation. Large organic ions are inserted between the layers of the crystal using a voltage, which weakens the interlayer forces.
Mild sonication then separates the layers into nanosheets without damaging their structure. These nanosheets are stable in suspension and retain lateral dimensions of over one micron. That is far larger than those typically produced by mechanical exfoliation.
The next step is assembly. The researchers prepare a silicon substrate with gold source and drain electrodes patterned on top of a thin aluminum oxide dielectric. They then apply an alternating current across selected electrode pairs while dropping the nanosheet solution onto the surface. The non-uniform electric field created by the electrodes draws the charged nanosheets into the gaps. This aligns them and creates continuous channels between the contacts. This method, known as alternating current dielectrophoresis (AC-DEP), allows for highly localized placement of materials without direct contact or masks.
The team optimized several aspects of the process. They found that using tapered electrodes improved the shape of the electric field and reduced stray deposition. They also identified 50 Hz as the ideal frequency for the AC signal. This balanced alignment efficiency and nanosheet adhesion. Short application times failed to create continuous channels, while excessively long times resulted in thick films that were harder to turn off electrically. A duration of 15 seconds produced channels about 10 nanometers thick with reliable coverage and uniformity.
Even high-quality 2D materials often suffer from atomic defects. In particular, vacancies where sulfur or selenium atoms are missing. These defects unintentionally dope the material, affecting its ability to behave cleanly as either n-type or p-type. To correct this, the researchers used a chemical treatment based on the superacid bis(trifluoromethane)sulfonimide (TFSI).
A single post-fabrication immersion in TFSI solution passivated these defects in both materials. This improved carrier mobility, reduced unintentional doping, and aligned the electrical characteristics of the n-type and p-type transistors.
After treatment, MoS₂ transistors reached average mobilities of 4.3 cm² per volt-second and on/off current ratios above 50,000. WSe₂ transistors achieved 3.0 cm² per volt-second and on/off ratios of 30,000. Both types of transistors operated at similar current levels and threshold voltages. This is a requirement for building balanced complementary logic circuits. Across an array of 30 devices, the team reported low variability in performance. This confirmed the reproducibility of the process.
With these components, the researchers constructed several fundamental logic gates. They created inverters (NOT gates), as well as NAND and NOR gates, which are essential for all digital logic. They also built a static random access memory (SRAM) cell by connecting two inverters in a cross-coupled configuration.
All devices functioned as expected. The inverters showed high voltage gain and reliable switching with low static power consumption. The logic gates produced the correct outputs for all input combinations. The SRAM cell retained its state after the input signal was removed.
The method avoids the need for lithographic patterning or selective doping. Both are difficult to scale in 2D material systems. Instead, it uses electric fields to guide materials into position with micron-scale precision. A single chemical treatment then optimizes performance. This combination of deterministic assembly and post-synthetic doping produces circuits that are functional, scalable, and manufactured under relatively simple conditions.
By focusing on process simplicity, reproducibility, and integration, the work represents a step toward using 2D semiconductors in practical circuit applications. The electric-field-guided assembly method developed here could be extended to other combinations of 2D materials. This would enable more complex circuits with better performance. It also offers a path to low-cost production of logic devices for applications where traditional silicon methods are too expensive, too rigid, or too complex.
Rather than relying on finer etching of silicon or more expensive fabrication equipment, this approach aims to make progress by placing materials where they are needed, in forms where they can function, using tools that support scale from the start.
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