A stacked chip captures, encrypts, and searches image data directly on hardware, combining photodetection, memory, and key generation for secure real-time processing in connected devices.
(Nanowerk Spotlight) Smart devices are embedded in everyday environments. Doorbells recognize visitors, streetlights count traffic, factory cameras monitor equipment, and phones track movement and identity. These are all part of the Internet of Things (IoT), a network of physical devices connected through software and sensors.
Many IoT applications rely on embedded systems known as edge devices. An edge device is any hardware that captures, processes, or analyzes data directly where it is collected instead of sending raw information to a central server. For tasks like detecting motion, recognizing faces, or validating access, the device must respond quickly and store or analyze data on the spot. It cannot wait for distant cloud servers to return results.
But edge devices have tight limits on size, power, and cost. They also handle sensitive information that creates new risks. The data they gather must be protected from the moment it arrives, not later in the cloud.
Traditional hardware falls short. Sensors, memory chips, processors, and encryption modules exist as separate parts and move data between them. That separation raises security risks and wastes power. Progress in chip stacking, low-temperature transistor manufacturing, and resistive memory has opened a path to rethink how these functions can work together in a compact, secure form.
Conceptual schematic of the multifunctional M3D sensory and ternary content-addressable memory (TCAM) system. a) Schematic of the human visual system, where early-stage pre-processing occurs in the retina, followed by parallel processing in the brain without built-in encryption mechanisms. b) Artificial neuromorphic systems are vulnerable to hardware-level threats, highlighting the need for near-sensor cryptographic operations and homomorphic engines capable of processing encrypted data without exposing the original information. c) Radar chart comparing key properties of thin-film transistor (TFT) channel materials considered for M3D integration. d) Schematic of the proposed M3D architecture featuring vertically stacked high-density VRRAM arrays (L1 and L2) and an IGZO TFT layer (L3). PbS quantum dots deposited on the IGZO channel enhance phototransistor responsivity to visible light. e) Generation of PUF keys from three independent entropy sources within the M3D sensory array for multi-layer encryption. f,g) Homomorphic associative computing based on near-sensor hashing in the M3D sensory array and encrypted data search in the TCAM array. (Image: Reproduced with permission by Wiley-VCH Verlag) (click on image to enlarge)
The system integrates three layers. The bottom two are vertical resistive random access memory (VRRAM). The top layer is a thin-film phototransistor made from a semiconductor called IGZO, short for indium gallium zinc oxide. The transistor is coated with lead sulfide quantum dots, which are tiny particles that absorb light and generate electrical charge. These dots extend the transistor’s light sensitivity from ultraviolet into the visible and infrared.
All three layers are fabricated monolithically on a silicon wafer under thermal conditions that protect the lower layers from damage.
When light hits the top layer, the quantum dots inject charge into the IGZO channel. That change in electrical conductance can be used to trigger or assist the switching of the VRRAM cells underneath. In other words, the chip does not just sense light. It uses light to help write data into memory. That allows raw visual information to be stored directly in the memory stack without extra circuits for digitizing or buffering the signal.
The VRRAM layers also act as a source of randomness for secure key generation. Each resistive memory cell has a different initial resistance after being reset because the conductive paths inside each device form in slightly different ways.
The phototransistor layer introduces two more independent variations: the voltage needed to turn the transistor on and the strength of its response to a fixed light level. The paper treats these three parameters as distinct randomness sources. Each one is used to create a digital key that is unique for every device.
Keys created from physical variation are called physically unclonable functions, or PUFs. They are used in hardware security to authenticate devices and protect data without storing secret numbers that could be extracted.
The study shows that the three keys generated by the chip have an average difference of about 50 percent between devices, which means each device produces a distinct and uncorrelated key. Combining the keys using logic operations such as exclusive OR, or XOR, further reduces the chance of modeling attacks, where an adversary tries to guess a key by studying many inputs and outputs.
Instead of storing full images, the chip reduces them into compact digital codes called hashes. It uses a method called locality sensitive hashing, or LSH. First, the analog resistance values of the two VRRAM layers are read out and subtracted. The sign of the result forms a single bit of the hash.
A group of these bits becomes a signature that captures key features of the original data. Two similar images will produce hash codes that differ in only a few positions. This property allows the device to compare stored data with incoming queries and judge how similar they are without ever exposing the original inputs.
To protect the hash, the chip encrypts it bit by bit using the XOR operation and a key derived from the PUF. The XOR method has a useful property. If two plaintext values are close to each other, then their encrypted versions will also be close, as long as the same key is used. This means the chip can search encrypted data for the most similar match without decrypting it.
The study verifies this behavior using a measure called matching probability and shows that the encrypted search preserves over 94 percent of the similarity pattern seen in the unencrypted case.
Large-scale search is handled by another part of the chip called content-addressable memory, or CAM. CAM is a type of memory that compares stored data with an input on the fly and returns a match signal without needing to check each entry one by one. This chip uses a ternary version of CAM, or TCAM, where each bit can store a 0, a 1, or an X that matches both. The stacked VRRAM and IGZO layers act together as a TCAM cell.
The IGZO layer switches on or off based on the stored bit, and the resulting current is used to decide whether the input and stored values match. This circuit design benefits from the low leakage of the IGZO layer and the compact footprint of the vertical stack.
The paper reports that the stacked TCAM achieves a more than ninefold improvement in area efficiency and a more than sixfold improvement in the combined metric of energy and speed when compared to a standard two-dimensional layout. These gains come from the vertical design, which shortens wiring paths and reduces the number of transistors needed.
To test a real task, the authors map small images of handwritten digits to 80-bit hashes using the chip and then classify them with a simple neural network. The accuracy falls by only two tenths of a percent when using the encrypted hashes instead of the plain ones. This shows that the encryption scheme preserves the data structure needed for basic machine learning.
The work demonstrates a way to capture, store, and protect visual information within a single piece of hardware. By building the sensor, memory, and security functions into a shared vertical stack, the chip reduces data movement and removes the need for external encryption units. The approach could support future edge devices that must treat visual data as sensitive from the moment it enters the system.
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